This invention relates to a binary data identification circuit which can be used in a circuit for, for example, normalizing a result of the operation of a floating-point processing and which is capable of detecting a digit position of an implied "1" of binary data and identifying a bit pattern of the binary data.
A result of the operation of a floating-point processing is normalized by detecting a digit position of a bit "1" (implied "1") first emerging when viewing an input operand in its MSB (most significant bit)-to-LSB (least significant bit) direction and logically shifting a bit or bits corresponding to a position or positions lower than that implied "1" position towards the MSB, in which case "0" is set to the remaining bit position or positions, including the implied "1" position. Now suppose that, for example, an n-bit mantissa data (binary data) having a bit pattern as shown in FIG. 1 is used as an input operand. In this case, detection is made of the bit position (i-1) corresponding to the bit "1" which first emerges when viewing the input operand in a direction from the MSB corresponding to the (n-1)th digit position to the LSB corresponding to the 0th digit position. Then those bits lower in position than the digit position (i-1), that is, those bits present in the (i-2)th to 0th positions are logically shifted to the MSB position. Then, a {(n-1)-(i-1)+1=n-i+1} number of bits lower in position than the (i-1) number of bits so logically shifted are all set to "0". In order to implement such normalization, use is made, in the prior art circuit, of barrel shifter 1 for shifting an input operand and shift control circuit 2 for generating shift control data for designating a logical shift position of barrel shifter 1, as shown in FIG. 2. Shift control circuit 2 includes priority encoder 2A and decoder 2B as shown, for example, in FIG. 2. Priority encoder 2A divides the input operand into, for example, m blocks each including 8 bits, detects the digit position of an implied "1" in each block and generates a binary code of 3.times.m bits representing the digit position detected. For this reason, the respective block of priority encoder 2A is comprised of eight input NAND gates for receiving eight bit signals, an output NAND gate for receiving the output signals of the input NAND gates and inverted replica of a control signal Ei which is an output signal E0 from the preceding block, three AND gates each having four input terminals selectively connected to the output terminals of the input NAND gates and three NOR gates for receiving the output signals of the AND gates and control signal Ei supplied through a corresponding buffer. In this connection it is to be noted that the MSB or a bit "0" of an input operand is supplied as the control signal Ei of the first stage block. This type of priority encoder is disclosed in detail in "Digital Circuits for Binary Arithmetic" by R. M. M. Oberman, pp 277 to 281. Therefore, any further explanation is omitted. This type of priority encoder is proved effective in detecting the digit position of an implied "1" and outputting binary data representing the digit position detected. To this end, however, a fairly great amount of hardware will be required. Where barrel shifter 1 is so arranged that the input operand is logically shifted by the number of bits corresponding to the shift control signal, it is necessary to decode binary data from priority encoder 2A by means of decoder 2B. In this case, a greater amount of hardware is required in constructing decoder 2B, thus resulting in a significant amount of hardware for shift control circuit 2.